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KM681000B Family
128K x8 bit Low Power CMOS Static RAM
FEATURES
U U
PRELIMINARY CMOS SRAM
GENERAL DESCRIPTION
The KM681000B family is fabricated by SAMSUNG's advanced CMOS process technology. The family can support various operating temperature ranges and have various package types for user flexibility of system design. The family also support low data retention voltage for battery back-up operation with low data retention current.
U
U
U
U
Process Technology : 0.6- CMOS Organization : 128Kx8 Power Supply Voltage : Single 5.0V 3/4 10% Low Data Retention Voltage : 2V(Min) Three state output and TTL Compatible Package Type : JEDEC Standard 32-DIP, 32-SOP, 32-TSOP I R/F
PRODUCT FAMILY
Power Dissipation Product Family KM681000BL KM681000BL-L KM681000BLE KM681000BLE-L KM681000BLI KM681000BLI-L Industrial(-40~85E) 70/100ns Extended(-25~85E) 70/100ns Operating Temperature Speed PKG Type Standby (ISB1, Max) 100E 20E 100E 50E 100E 50E 70mA Operating (ICC2)
Commercial(0~7E)
55/70ns
32-DIP,32-SOP 32-TSOP I R/F 32-SOP 32-TSOP I R/F 32-SOP 32-TSOP I R/F
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
A0~3, A8~11
N.C A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27
VCC A15 CS2 WE A13 A8 A9 A11 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4
32-DIP 32-SOP
26 25 24 23 22 21 20 19 18 17
A11 A9 A8 A13 WE CS2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
32-TSOP Type I - Forward
OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3
Y-Decoder
X-Decoder
A4~7, A12~16
Cell Array
Control Logic
CS1,CS2 WE,OE
I/O1~8
A4 A5 A6 A7 A12 A14 A16 NC VCC A15 CS2 WE A13 A8 A9 A11
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22
I/O Buffer
32-TSOP Type I-Reverse
23 24 25 26 27 28 29 30 31 32
A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 CS1 A10 OE
Name
A0~A16 WE
Function
Address Inputs Write Enable Input Chip Select Inputs Output Enable Input Data Inputs/Outputs Power Ground No Connection
CS1,CS2
OE I/O1~I/O18 Vcc Vss N.C
Revision 0.3 April 1996
KM681000B Family
PRODUCT LIST & ORDERING INFORMATION
PRODUCT LIST
Commercial Temp Product (0~70E) Part Name
KM681000BLP-5 KM681000BLP-5L KM681000BLP-7 KM681000BLP-7L KM681000BLG-5 KM681000BLG-5L KM681000BLG-7 KM681000BLG-7L KM681000BLT-5 KM681000BLT-5L KM681000BLT-7 KM681000BLT-7L KM681000BLR-5 KM681000BLR-5L KM681000BLR-7 KM681000BLR-7L
PRELIMINARY CMOS SRAM
Extended Temp Products (-25~85E) Part Name
KM681000BLGE-7 KM681000BLGE-7L KM681000BLGE-10 KM681000BLGE-10L KM681000BLTE-7 KM681000BLTE-7L KM681000BLTE-10 KM681000BLTE-10L KM681000BLRE-7 KM681000BLRE-7L KM681000BLRE-10 KM681000BLRE-10L
Industrial Temp Products (-40~85E) Part Name
KM681000BLGI-7 KM681000BLGI-7L KM681000BLGI-10 KM681000BLGI-10L KM681000BLTI-7 KM681000BLTI-7L KM681000BLTI-10 KM681000BLTI-10L KM681000BLRI-7 KM681000BLRI-7L KM681000BLRI-10 KM681000BLRI-10L
Function
32-DIP,55ns,L-pwr 32-DIP,55ns,LL-pwr 32-DIP,70ns,L-pwr 32-DIP,70ns,LL-pwr 32-SOP,55ns,L-pwr 32-SOP,55ns,LL-pwr 32-SOP,70ns,L-pwr 32-SOP,70ns,LL-pwr 32-TSOP F,55ns,L-pwr 32-TSOP F,55ns,LL-pwr 32-TSOP F,70ns,L-pwr 32-TSOP F,70ns,LL-pwr 32-TSOP R,55ns,L-pwr 32-TSOP R,55ns,LL-pwr 32-TSOP R,70ns,L-pwr 32-TSOP R,70ns,LL-pwr
Function
32-SOP,70ns,L-pwr 32-SOP,70ns,LL-pwr 32-SOP,100ns,L-pwr 32-SOP,100ns,LL-pwr 32-TSOP F,70ns,L-pwr 32-TSOP F,70ns,LL-pwr 32-TSOP F,100ns,L-pwr 32-TSOP F,100ns,LL-pwr 32-TSOP R,70ns,L-pwr 32-TSOP R,70ns,LL-pwr 32-TSOP R,100ns,L-pwr 32-TSOP R,100ns,LL-pwr
Function
32-SOP,70ns,L-pwr 32-SOP,70ns,LL-pwr 32-SOP,100ns,L-pwr 32-SOP,100ns,LL-pwr 32-TSOP F,70ns,L-pwr 32-TSOP F,70ns,LL-pwr 32-TSOP F,100ns,L-pwr 32-TSOP F,100ns,LL-pwr 32-TSOP R,70ns,L-pwr 32-TSOP R,70ns,LL-pwr 32-TSOP R,100ns,L-pwr 32-TSOP R,100ns,LL-pwr
ORDERING INFORMATION
KM6 8 X 1000 B X X X - XX X L-Low Low Power, Blank-Low Power or High Power Access Time : 5=55ns, 7=70ns, 10=100ns Operating temperature : Blank=Commerial, I=Industrial, E=Extended, Package Type : P-DIP, G=SOP, T=TSOP Forward, R=TSOP Reverse L-Low Power or Low Low Power, Blank-High Power Die Version : B=3 rd generation Density : 1000=1Mbit Bank=5V, V=3.0~3.6V, U=2.7~3.3V Organization : 8=x8 SEC Standard SRAM
Revision 0.3 April 1996
KM681000B Family
ABSOLUTE MAXIMUM RATINGS*
Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Symbol VIN,VOUT VCC PD TSTG Ratings -0.5 to 7.0 -0.5 to 7.0 1.0 -65 to 150 0 to 70 Operating Temperature TA -25 to 85 -40 to 85 Soldering temperature and time TSOLDER 260E, 10sec (Lead Only) Unit V V W E E E E -
PRELIMINARY CMOS SRAM
Remark KM681000BL/L-L KM681000BLE/LE-L KM681000BLI/LI-L -
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stres s rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS *
Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Min 4.5 0 2.2 -0.5*** Typ** 5.0 0 Max 5.5 0 Vcc+0.5 0.8 Unit V V V V
* 1) Commercial Product : TA=0 to 70E, unless otherwise specified 2) Extended Product : TA=-25 to 85E, unless otherwise specified 3) Industrial Product : TA=-40 to 85E, unless otherwise specified ** TA=25E *** VIL(min)=-3.0V for A 50ns pulse width
CAPACITANCE* (f=1MHz, TA=25E)
Item Input capacitance Input/Output capacitance
* Capacitance is sampled not 100% tested
Symbol CIN CIO
Test Condition Vin=0V Vio=0V
Min -
Max 6 8
Unit pF pF
Revision 0.3 April 1996
KM681000B Family
DC AND OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply current Symbol ILI ILO ICC ICC1 Average operating current ICC2 Output low voltage Output high voltage Standby Current(TTL) KM681000BL KM681000BL-L Standby Current (CMOS) KM681000BLE KM681000BLE-L KM681000BLI KM681000BLI-L ISB1 VOL VOH ISB Test Conditions* VIN=Vss to Vcc CS1=VIH or CS2=VIL or WE=VIL, VIO=Vss to Vcc CS1=VIL, CS2=VIH, VIN=VIH or VIL, IIO=0mA Cycle time=1A 100% duty CS1A0.2V, CS2AVCC-0.2V IIO=0mA CS1=VIL,CS2=VIH Min cycle, 100% duty IOL=2.1mA IOH=-1.0mA CS1=VIH, CS2=VIL L (Low Power) LL (Low Low Power) L (Low Power) LL (Low Low Power) L (Low Power) LL (Low Low Power)
PRELIMINARY CMOS SRAM
Mi -1 -1 2.4 Typ** 7 Max 1 1 15** 10*** 70 0.4 3 100 20 100 50 100 50 Unit
E E
mA mA mA V V mA
CS1AVcc-0.2V CS2AVcc-0.2V or CS2A0.2V Other input=0~Vcc
E E E E E E
* 1) Commercial Product : TA=0 to 70E, Vcc=5.0V3/410%, unless otherwise specified 2) Extended Product : TA=-25 to 85E, Vcc=5.0V3/410%, unless otherwise specified 2) Industrial Product : TA=-40 to 85E, Vcc=5.0V3/410%, unless otherwise specified ** 20mA for Exteneded and Industrial Products *** 15mA for Extended and Industrial Products
A.C CHARACTERISTICS
TEST CONDITIONS(1.Test Load and Test Input/Output Reference)*
Item Input pulse level Input rising & falling time input and output reference voltage Output load (See right)
* See DC Operating conditions
Value 0.8 to 2.4V 5ns 1.5V CL=100pF+1TTL
Remark * Including scope and jig capacitance CL*
Revision 0.3 April 1996
KM681000B Family
TEST CONDITIONS(2. Temperature and Vcc Conditions)
Product Family KM681000BL/L-L KM681000BLE/LE-L KM681000BLI/LI-L Temperature 0~70E -25~85E -40~85E Power Supply(Vcc) 5.0V3/410% 5.0V3/410% 5.0V3/410% Speed Bin 55/70ns 70/100ns 70/100ns
PRELIMINARY CMOS SRAM
Comments Commercial Extended Industrial
PARAMETER LIST FOR EACH SPEED BIN
Speed Bins Parameter List Symbol 55ns Min Read Read cycle time Address access time Chip select to output Output enable to valid output Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change Write Write cycle time Chip select to end of write Address set-up time Address valid to end of write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z Max 55 55 25 20 20 20 Min 70 10 5 0 0 10 70 60 0 60 50 0 0 30 0 5 70ns Max 70 70 35 25 25 25 100ns Min 100 10 5 0 0 10 100 80 0 80 60 0 0 40 0 5 Max 100 100 50 30 30 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
tRC tAA tCO1,tCO2 tOE tLZ1,tLZ2 tOLZ tHZ1,tHZ2 tOHZ tOH tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW
55 10 5 0 0 10 55 45 0 45 40 0 0 25 0 5
Revision 0.3 April 1996
KM681000B Family
DATA RETENTION CHARACTERISTICS
Item Vcc for data retention VDR KM681000BL KM681000BL-L Data retention current IDR KM681000BLE KM681000BLE-L KM681000BLI KM681000BLI-L Data retention set-up time Recovery time Vcc=3.0V CS1AVcc-0.2V Symbol Test Condition* CS1***AVcc-0.2V L-Ver LL-Ver L-Ver LL-Ver L-Ver LL-Ver See data retention waveform Min 2.0 0 5
PRELIMINARY CMOS SRAM
Typ** 1 0.5 Max 5.5 50 10 50 25 50 25 ms Unit V
E
tRDR tRDR
* 1) Commercial Product : TA=0 to 70E, unless otherwise specified 2) Extended Product : TA=-25 to 85E, unless otherwise specified 2) Industrial Product : TA=-40 to 85E, unless otherwise specified ** TA=25E *** CS1AVCC-0.2V,CS2AVCC-0.2V(CS1 controlled) or CS2A0.2V(CS2 controlled)
DATA RETENTION TIMING DIAGRAM
1) CS1 Controlled
tSDR
Data Retention Mode
tRDR
VCC 4.5V
2.2V VDR CS1A VCC - 0.2V CS1 GND
2) CS2 controlled
Data Retention Mode VCC
4.5V CS2
tSDR tRDR
VDR CS2 0.4V GND
A 0.2V
Revision 0.3 April 1996
KM681000B Family
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE (1) (Address Controlled)
(CS1=OE=VIL, CS2= WE= VIH)
PRELIMINARY CMOS SRAM
tRC
Address
tAA tOH
Data Out
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE (WE=VIH)
tRC
Address
tOH tAA tCO1
CS1
CS2
tCO2 tHZ(1,2)
OE
tOLZ
tOE
tOHZ
Data out
High-Z
tLZ
Data Valid
NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage le vels. 2. At any given temperature and voltage condition, tHZ(max.) is less than tLZ(min.) both for a given device and from device to device.
Revision 0.3 April 1996
KM681000B Family
TIMING WAVEFORM OF WRITE CYCLE (1) Controlled) (WE
tWC
PRELIMINARY CMOS SRAM
Address
tWR1(4) tCW(2)
CS1
tAW
CS2
tCW(2)
WE
tAS(3)
tWP(1)
tDW
tDH
Data in
Data Valid
tWHZ
tOW
Data out
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE (2) Controlled) (CS1
tWC
Address
tWR1(4) tAS(3) tCW(2)
CS1
tAW
CS2
tWP(1)
WE
tDW
tDH
Data in
Data Valid
Data out
High-Z
High-Z
Revision 0.3 April 1996
KM681000B Family
TIMING WAVEFORM OF WRITE CYCLE (2) Controlled) (CS2
PRELIMINARY CMOS SRAM
tWC
Address
tWR2(4) tAS(3) tCW(2)
CS1
tAW
CS2
tCW(2) tWP(1)
WE
tDW
tDH
Data in
Data Valid
Data out NOTES (WRITE CYCLE)
High-Z
High-Z
1. A write occurs during the overlap of low CS1, high CS2 and low WE. A write begins at the latest transition among CS1 going low, CS2 going high and WE going low. A write ends at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP is measured from the beginning or write to the end of write. 2. tCW is measured from the later of CS1 going low or CS2 going high to the end of write. 3. tAS is measured from the address calid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends at CS1, or WE going high, tWR2 applied in case a write ends at CS2 going to low.
FUNCTIONAL DESCRIPTION
CS1 H X L L L
* X means don't care
CS2 X L H H H
WE X X H H L
OE X X H L X
Mode Power Down Power Down Output Disable Read Write
I/O Pin High-Z High-Z High-Z Dout Din
Current Mode ISB,ISB1 ISB,ISB1 ICC ICC ICC
Revision 0.3 April 1996
KM681000B Family
PACKAGE DIMENSIONS
32 DUAL INLINE PACKAGE (600mil)
PRELIMINARY CMOS SRAM
Units :MillimeterS(Inches)
+0.10 -0.05 0.010+0.004 -0.002
0.25
#32
#17
13.60 3/4 0.20 0.535 3/4 0.008
#1 42.31 1.666 MAX 4.191 3/4 0.20 1.650 3/4 0.008
#16 3.81 3/4 0.20 0.150 3/4 0.008 5.08 0.200 MAX
15.24 0.600
0~15E
(
1.91 ) 0.075
0.46 3/4 0.10 0.018 3/4 0.004 1.52 3/4 0.10 0.060 3/4 0.004
2.54 0.100
3.30 3/4 0.30 0.130 3/4 0.012 0.38 MIN 0.015
32 PLASTIC SMALL OUTLINE PACKAGE (525mil)
0~8E #32 #17
14.12 3/4 0.30 0.556 3/4 0.012
11.43 3/4 0.20 0.450 3/4 0.008
#1 20.87 MAX 0.822 20.47 3/4 0.20 0.806 3/4 0.008
#16 2.74 3/4 0.20 0.108 3/4 0.008 3.00 0.118 MAX
13.34 0.525 0.80 3/4 0.20 0.031 3/4 0.008
0.20 +0.10 -0.05 0.008+0.004 -0.002
0.10 MAX 0.004 MAX
+0.100 -0.050 0.016 +0.004 -0.002
( 0.71 ) 0.028
0.41
1.27 0.050
0.05 0.002 MIN
Revision 0.3 April 1996
KM681000B Family
PACKAGE DIMENSIONS
32 THIN SMALL OUTLINE PACKAGE TYPE I (0820F)
PRELIMINARY CMOS SRAM
Units :MillimeterS(Inches)
+0.10 -0.05 +0.004 0.008-0.002
0.20
20.00 3/4 0.20 0.787 3/4 0.008 #32 ( 8.00 0.315 0.25 ) 0.010
#1
8.40 0.331 MAX
0.50 0.0197
#16
#17 1.00 3/4 0.10 0.039 3/4 0.004 1.20 MAX 0.047
+0.10 -0.05 0.006+0.004 -0.002
0.05 0.002 MIN
0.25 0.010 TYP
18.40 3/4 0.10 0.724 3/4 0.004
0.15
0~8E
0.45 ~0.75 0.018 ~0.030
(
0.50 ) 0.020
32 THIN SMALL OUTLINE PACKAGE TYPE I (0820R)
0.20
+0.10 -0.05 0.008+0.004 -0.002
20.00 3/4 0.20 0.787 3/4 0.008 #17 ( 8.40 0.331 MAX 8.00 0.315 0.25 ) 0.010
#16
0.50 0.0197
#1
#32 1.00 3/4 0.10 0.039 3/4 0.004 1.20 0.047 MAX 0.05 0.002 MIN
0.25 0.010 TYP
18.40 3/4 0.10 0.724 3/4 0.004
0~8E
0.45 ~0.75 0.018 ~0.030
(
0.50 ) 0.020
0.10 MAX 0.004 MAX
+0.10 -0.05 0.006 +0.004 -0.002
0.15
0.004 MAX 1.10 MAX
Revision 0.3 April 1996

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